Friday, September 7, 2012
Tuesday, September 4, 2012
VLSI Final Projects
Posted by Unknown in: Education Important Projects and Abstracts
VLSI
1.Design of a Bus Bridge between OCP to AHB
INDEX
PROJECT
2.Design and implementation of error detection and error correction
INDEX
PROJECT
3. DESIGN AND IMPLEMENTATION OF DIFFERENT ADDERS USING VHDL
INDEX
PROJECT
4.Design and implementation of sequence detector
INDEX
PROJECT
5.Implementation of traffic light controller using VHDL
INDEX
PROJECT
6.A Robust UART architecture based on recursive running for better running nice performance
INDEX
PROJECT
7.Implementation Of FFTIFFT Blocks for Orthogonal Frequency Division
INDEX
PROJECT
8.Effective implementation of ATM Controller
INDEX
PROJECT
9.An efficient implementation of floating point multiplier
INDEX
PROJECT
10.Design and Implementation of SPI Slave Device on FPGA
INDEX
PROJECT
11.Design of a On chip bus with OCP interface
INDEX
PROJECT
12.Implementation of asynchronous pointer comparisons based FIFO design
INDEX
PROJECT
13.Design and implementation of seven segment decoder and biderectional shift register using VHDL
INDEX
PROJECT
14.Design and implementation of 8 point FFT
INDEX
PROJECT
15.High peformance complex number multiplier using booth wallace algorithm
INDEX
PROJECT
1.Design of a Bus Bridge between OCP to AHB
INDEX
PROJECT
2.Design and implementation of error detection and error correction
INDEX
PROJECT
3. DESIGN AND IMPLEMENTATION OF DIFFERENT ADDERS USING VHDL
INDEX
PROJECT
4.Design and implementation of sequence detector
INDEX
PROJECT
5.Implementation of traffic light controller using VHDL
INDEX
PROJECT
6.A Robust UART architecture based on recursive running for better running nice performance
INDEX
PROJECT
7.Implementation Of FFTIFFT Blocks for Orthogonal Frequency Division
INDEX
PROJECT
8.Effective implementation of ATM Controller
INDEX
PROJECT
9.An efficient implementation of floating point multiplier
INDEX
PROJECT
10.Design and Implementation of SPI Slave Device on FPGA
INDEX
PROJECT
11.Design of a On chip bus with OCP interface
INDEX
PROJECT
12.Implementation of asynchronous pointer comparisons based FIFO design
INDEX
PROJECT
13.Design and implementation of seven segment decoder and biderectional shift register using VHDL
INDEX
PROJECT
14.Design and implementation of 8 point FFT
INDEX
PROJECT
15.High peformance complex number multiplier using booth wallace algorithm
INDEX
PROJECT
EMBEDDED SYSTEMS
Posted by Unknown in: Education Important Projects and Abstracts
EMBEDDED SYSTEMS
1.IR BASED APPLIANCES CONTROL SYSTEM
INDEX
PROJECT
2.Bank Security system
INDEX
PROJECT
3.Automatic railway gate control system
INDEX
PROJECT
4.ADVANCED INDOOR ROOM LIGHT CONTROL
INDEX
PROJECT
5.ADVANCED DENSITY BASED TRAFFIC LIGHT CONTROLLING SYSTEM
INDEX
PROJECT
6.NIGHT LIGHT SAVER
INDEX
PROJECT
7.OBSTACLE DETECTION AND AVOIDANCE ROBOT
INDEX
PROJECT
8.Advance security system usinf RF
INDEX
PROJECT
9.TRAFFIC LIGHT PRIORITY CONTROL FOR EMERGENCY VEHICLES
INDEX
PROJECT
10.AUTOMATIC STREET LIGHT CONTROLLER WITH RTC
INDEX
PROJECT
1.IR BASED APPLIANCES CONTROL SYSTEM
INDEX
PROJECT
2.Bank Security system
INDEX
PROJECT
3.Automatic railway gate control system
INDEX
PROJECT
4.ADVANCED INDOOR ROOM LIGHT CONTROL
INDEX
PROJECT
5.ADVANCED DENSITY BASED TRAFFIC LIGHT CONTROLLING SYSTEM
INDEX
PROJECT
6.NIGHT LIGHT SAVER
INDEX
PROJECT
7.OBSTACLE DETECTION AND AVOIDANCE ROBOT
INDEX
PROJECT
8.Advance security system usinf RF
INDEX
PROJECT
9.TRAFFIC LIGHT PRIORITY CONTROL FOR EMERGENCY VEHICLES
INDEX
PROJECT
10.AUTOMATIC STREET LIGHT CONTROLLER WITH RTC
INDEX
PROJECT
Monday, September 3, 2012
Saturday, September 1, 2012
GATE ELECTRONIC AND COMMUNICATION ENGINEERING (EC)SUBJECT WISE MARKS WEIGHTAGE
Weightage of Marks in GATE (Subject-wise) | GATE – EC (Electronics & Communication Engineering)
Examination Type:
GATE Examination consists of a single paper of 3 Hours duration, which contains 65 Questions carrying a maximum of 100 Marks. The Question paper will consist of only multiple choice objective questions
Note: GATE 2013 score is valid for 2 YEARS from the date of announcement of the GATE 2013 results
.
Weightage of Marks in GATE (Subject-wise) | GATE – EC (Electronics & Communication Engineering)
Examination Type:
GATE Examination consists of a single paper of 3 Hours duration, which contains 65 Questions carrying a maximum of 100 Marks. The Question paper will consist of only multiple choice objective questions
Subject
|
1 mark
Questions
|
2 mark
Questions
|
Total
marks
|
Engineering mathematics
|
3-6
|
3-8
|
9-22
|
Networks
|
0-5
|
4-7
|
10-18
|
Electronic devices
|
2-5
|
3-8
|
8-20
|
Analog circuits
|
0-5
|
5-11
|
12-25
|
Digital circuits
|
0-5
|
5-8
|
13-19
|
Microprocessors
|
0-1
|
1-4
|
1-8
|
Signals & systems
|
2-5
|
3-8
|
9-18
|
Control systems
|
1-3
|
4-9
|
10-21
|
Electromagnetics
|
1-2
|
3-8
|
8-18
|
Paper
Code
|
Pattern of question papers
|
Negative marks for wrong answer
|
Q.1 TO 1.25:will carry one mark each
(sub-total 25 marks)
|
1/3 mark will be deducted for each wrong answer
| |
Q.26 TO Q.55:will carry two marks each
(sub-total 60 marks)
|
2/3 mark will be deducted for each wrong answer
| |
Q.48 THROUGH Q.51 (2 pairs) will becommon
Data questions: each will carry two marks
|
2/3 mark will be deducted for each wrong answer
| |
CS,EC
IN,EE
CE,ME
|
Question pairs (Q.52, Q.53)
(Q.54, Q.55) will be linked answer questions.
The answer to the second question of the last two pairs will depend on the answer to the first question of the pair.If the first question in the linked pair is wrongly answered or is un-attempted, then the answer to the second question in the pair will not be evaluated. Each question will carry two marks |
There will be negative marks only for wrong answer to the first question of the linked answer question pair i.e. for Q.52 and Q.54, 2/3 mark will be deducted for each wrong answer. There is no negative marking for Q.53 and Q.55
|
Q.56 to Q.60: From General Aptitude (GA) will carry one mark each (sub-total 5 marks)
|
1/ 3 mark will be deducted for each wrong answer.
| |
Q.61 to Q.65 : From GA will carry two marks each (sub-total 10 marks)
|
2/3 mark will be deducted for each wrong answer.
| |
All the papers bearing the codes CS, EC, EE, IN, CE, ME will contain few questions on
Engineering Mathematics carrying 15 marks.
| ||
Note: GATE 2013 score is valid for 2 YEARS from the date of announcement of the GATE 2013 results
.